Senior FPGA Developer (SystemVerilog)

Terraquantum · Remote · Remote

Employment typeContract
Experience levelSenior
Salary signalSalary not listed
Last checkedJust now
Source valid throughNov 6, 2026

Role Overview

<div class="content-intro"><img src="https://i.imgur.com/XN94Hg4.png" alt="" width="900" style="max-width: 100%;">  </div>The Role  The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end‑to‑end RTL ownership on AMD/Xilinx (Artix‑7, Kintex UltraScale): architect, implement, verify, and close timing on high‑rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer.  The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring‑up, and deliver reproducible, versioned bitstreams.  The Responsibilities  The Senior FPGA Developer should expect to work in the following activities.  <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">RTL architecture, interfaces, and rather high-speed datapaths <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Owning SystemVerilog RTL architecture/implementation for Artix‑7 and Kintex UltraScale (SystemVerilog, Vivado)</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third‑party MAC/PCS IP</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low‑level protocols —  and bridging them to high‑throughput interfaces (DDR/PCIe)</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Defining clear AXI/AXI‑Stream boundaries and register maps for SW/FW integration </li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Constraints, timing closure, and floorplanning <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin </li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Verification and CI <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Establishing a professional verification environment with ModelSim/Questa; developing self‑checking testbenches and regression suites; integrating Python/cocotb co‑simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as appropriate)</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW‑in‑the‑loop smoke tests </li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Bring-up, debug, and releases <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Board bring-up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring-up</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts </li> </ul> </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Cross-team collaboration and mentoring <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Driving system integration with SW/FW: register/driver contracts, throughput/latency budgets, HIL</li> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Mentoring a junior engineer; codifying style guides, reviews, and design documentation </li> </ul> </li> </ul>   The Requirements  The Senior FPGA Developer is expected to have the following qualifications and experience.  <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1">5+ years production FPGA on AMD/Xilinx; expert SystemVerilog RTL </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1">Demonstrated mentoring of junior engineers </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="15" data-aria-level="1">Strong constraints/timing (XDC), CDC/reset, and practical floorplanning; consistent timing closure </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="16" data-aria-level="1">Hands‑on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third‑party MAC/PCS IP </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="17" data-aria-level="1">Strong verification background; experience with self-checking testbenches and regression testing, proficiency with ModelSim/Questa. Knowledge of OSVVM/UVM is a plus </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="18" data-aria-level="1">CI for HDL: scripted sim/synth/impl (Tcl/Make/Python), lint, artifact/version management; board bring‑up and ILA‑based debug </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="19" data-aria-level="1">System integration with SW/FW: register maps, driver contracts, HIL </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="20" data-aria-level="1">Proficiency in written and spoken English </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="21" data-aria-level="1">Ability to be on-site in Munich or Potsdam offices to work with hardware, when required</li> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="21" data-aria-level="1">Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship. </li> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="21" data-aria-level="1">Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.</li> </ul> Good to have:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="22" data-aria-level="1">AXI4/AXI‑Stream expertise and DMA performance tuning </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="23" data-aria-level="1">Formal verification exposure </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="24" data-aria-level="1">Scripting for automation (Python/Tcl) and CI systems (GitHub Actions/Jenkins) </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="25" data-aria-level="1">MicroBlaze/Zynq ecosystems and low‑level FW/C driver collaboration </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="26" data-aria-level="1">Proven delivery on Artix‑7 and/or Kintex UltraScale with Vivado   </li> </ul><div class="content-conclusion">The Rewards  We are an international team of quantum technology experts and dedicated business creatives that are working to bring quantum-enabled solutions to the global market. Our brilliant team members enjoy a high degree of freedom working remotely or joining one of our office spaces. We have a vibrant, enthusiastic, passionate and creative culture driven by trust, excellence and continuous improvement. If you join the Terra Quantum team, you can expect:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">An opportunity to work with some of the brightest minds in the pioneering field of Quantum Technologies as well as an experienced and progressive Leadership team</li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">Gain knowledge of some of the most cutting-edge technology developments in science & engineering </li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">A chance to be part of one of Europe’s leading technology firms of the upcoming decades</li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">Welcoming, friendly, and professional colleagues</li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">A personal development plan with clear goals for advancement</li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">A competitive salary </li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">Flexible working arrangements </li> <li data-leveltext="" data-font="Symbol" data-listid="21" data-aria-posinset="1" data-aria-level="2">A diverse and supportive atmosphere, where innovation and initiative are encouraged  </li> </ul> If you are enthusiastic about positively impacting the world and helping to drive the second quantum revolution, let’s talk!    Company description  Quantum technologies have the potential to solve some of the world’s biggest challenges. There have been great advances in all areas of quantum technologies, and new fields of application are opened up every day. Hybrid computer systems that combine classic high-performance computing with quantum computers are already being used to develop solutions in sectors such as logistics, healthcare, finance, energy, automotive and aerospace. Quantum mechanical predictions are also used to obtain unprecedented precision in measurements, generate unbreakable codes, and form the basis of impenetrable communication networks. All these developments are happening right now, and they are happening at Terra Quantum.  At Terra Quantum we are building the world’s leading Quantum Technology company. We offer customers world-class quantum technology expertise organized as “quantum-as-a-service”: hybrid quantum algorithms, quantum compute and quantum enabled security solutions. Through the proprietary quantum cloud, customers have access to a unique technology platform which provides a toolset to solve real-world challenges in the realms of machine learning, optimization and simulation, today. In 2022, the company closed its Series A financing round with a $75m fundraise.  Quantum physics has, in some respects, parallels to the machine language of our computers-the zeros and ones into which our keyboard or touchscreen instructions are translated for execution in the computer-only on a larger scale: it is the machine language of the universe. The second quantum revolution is based on the control of individual quantum systems, such as individual atoms. We use quantum computers to solve currently unsolvable problems, simulate molecules and their interactions, find drugs for diseases that are not yet curable, find new materials, or make artificial intelligence stronger. Quantum is now.  Terra Quantum is a future-focused quantum services and technology company working on making the second quantum revolution a reality. Terra Quantum’s activities span all areas, markets, and industries globally.  <ul> <li>Our purpose is to pioneer quantum technologies to change the world for good,</li> <li>Our vision is to lead the quantum revolution and be the trailblazer in technology solutions, shaping a better future for humankind to thrive in, and</li> <li>Our mission is to unleash the power of quantum tech to deliver meaningful solutions today</li> </ul> Terra Quantum is an equal opportunities employer, committed to diversity, inclusion and employee well-being. </div> Find more English Speaking Jobs in Germany on Arbeitnow

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Senior FPGA Developer (SystemVerilog)

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